A Turn Model Based Router Design for 3D Network on Chip

Network on chip (NoC) is emerging as a new trend for a System on chip (SoC) design. The key advantages of NoC are high performance and scalability. Despite those improvements over the conventional shared-bus based systems, NoC are not shown as the ideal solution for the future SoC. Recently, with the three dimension (3D) technology. The 3D NoC has been designed to overcome the high power consumption, highcost communication and low throughput. This paper present a 3D router design which can support seven requests simultaneously. The traditional Turn Model technique used in 2D NoC has been extended in the case of 3D NoC in order to avoid deadlock conflicts. Experimental results in terms of area, power and clock frequency, relatively to 2D NoC and others famous 3D routers has been discussed.